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? semiconductor components industries, llc, 2009 may, 2009 ? rev. 0 1 publication order number: NCP5623C/d NCP5623C triple output i2c controlled rgb led driver the NCP5623C mixed analog circuit is a triple output led driver dedicated to the rgb illumination or backlight lcd display. the built ? in dc/dc converter is based on a high efficient charge pump structure with operating mode 1x and 2x. it provides a 94% peak efficiency. the tiny package makes the device suitable for room limited portable applications. features ? 2.7 to 5.5 v input voltage range ? rgb function fully supported ? programmable integrated gradual dimming ? 90 ma output current capability ? 94% peak efficiency ? built ? in short circuit protection ? provides three independent led drives ? support i2c protocol ? embedded ovp / open load protection ? this is a pb ? free device typical applications ? multicolor illuminations ? portable back light ? digital cellular phone camera photo flash ? lcd and key board simultaneous drive c3 220 nf d3 d2 d1 c2 gnd c1 gnd sda r1 62 k gnd scl gnd +vbat +vcc gnd mcu i2c port c1p 1 vbat 11 agnd 6 sda 7 scl 9 iref 8 gnd 2 led1 5 led2 4 led3 3 vout 10 c1n 12 u1 NCP5623C figure 1. typical multiple white led driver 1 f/10 v 1 f/6.3 v gnd http://onsemi.com 1 device package shipping ? ordering information NCP5623Cmutbg llga12 (pb ? free) 3000/tape & reel llga12 mu suffix case 513aa ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. (top view) agnd led1 led2 led3 gnd sda iref scl vout vbat cin cip pin assignment marking diagram gu = specific device code m = date code = pb ? free package gum 2 6 11 7 1 (note: microdot may be in either location)
NCP5623C http://onsemi.com 2 c3 220 nf vout d1 d2 d3 c2 gnd gnd vbat c1 gnd sda r1 62 k gnd dc/dc converter charge pump digital control over voltage pwm led#1 current NCP5623C vbat vbat agnd scl pwm led#2 pwm led#3 functions gnd gnd gnd gnd led1 led2 led3 vbat figure 2. simplified block diagram analog 1 f/6.3 v 1.0 f/10 v mirrors 11 6 8 7 9 1 12 10 3 4 5 2
NCP5623C http://onsemi.com 3 pin assignment pin name type description 1 c1p power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1n, pin 12 (note 1). 2 gnd power this pin is the ground signal for the analog and digital blocks and must be connected to the system ground. this pin is the ground reference for the dc/dc converter and the output current control. the pin must be connected to the system ground, a ground plane being strongly recommended. 3 led3 input, power this pin sinks to ground and monitors the current flowing into the led3, intended to be used in illu- mination application (note 2). the anode of the associated led shall be connected to the vout pin. 4 led2 input, power this pin sinks to ground and monitors the current flowing into the led2, intended to be used in illu- mination application (note 2). the anode of the associated led shall be connected to the vout pin. 5 led1 input, power this pin sinks to ground and monitors the current flowing into the led1, intended to be used in illu- mination application (note 2). 6 agnd analog ground this pin copies the analog ground and must be connected to the system ground plane. 7 sda input, digital this pin carries the data provided by the i2c protocol. the content of the sda byte is used to pro- gram the mode of operation and to set up the output current (note 1). 8 i ref input, analog this pin provides the reference current, based on the internal band ? gap voltage reference, to control the output current flowing in the led. a 1% tolerance, or better, resistor shall be used to get the highest accuracy of the led biases. an external current mirror can be used to bias this pin to dynam- ically set up the i ? led peak current. in no case shall the voltage at i ref pin be forced either higher or lower than the 600 mv provided by the internal reference. 9 scl input, digital this pin carries the i2c clock to control the charge pump converter and to set up the output current. the scl clock is associated with the sda signal. 10 vout output, power this pin provides the output voltage supplied by the charge pump converter. the vout pin must be bypassed by 1 f ceramic capacitor located as close as possible to the v out pin to properly bypass the output voltage to ground. the circuit shall not operate without such bypass capacitor connected across the vout pin and ground (note 1). the output voltage is internally clamped to 5.5 v maximum in the event of a no load situation. on the other hand, the output current is limited to 40 ma (typical) in the event of a short circuit to ground. 11 vbat input, power this pin is the input battery voltage to supply the analog and digital blocks. the pin must be de- coupled to ground by a 1 f or higher ceramic capacitor (note 1). 12 c1n power one side of the external charge pump capacitor (c fly ) is connected to this pin, associated with c1p, pin 1 (note 1) 1. using low esr ceramic capacitor, x5r type, is mandatory to optimize the charge pump efficiency and to reduce the emi. 2. the peak current is 37 ma for each led, the total charge pump output dc current being limited to 75 ma
NCP5623C http://onsemi.com 4 maximum ratings symbol rating value unit v bat power supply (see figure 3) ? 0.3 < vbat < 7.0 v vout output power supply 7.0 v sda, scl, shdi2c digital input voltage digital input current ? 0.3 < v < v bat 1 v ma esd human body model: r = 1500 , c = 100 pf (note 3) machine model 2 200 kv v p d r jc r ja llga12 package power dissipation @ t a = +85 c (note 4) thermal resistance junction to case thermal resistance junction to air 200 51 200 mw c/w c/w t a operating ambient temperature range ? 40 to +85 c t j operating junction temperature range ? 40 to +125 c t jmax maximum junction temperature +150 c t stg storage temperature range ? 65 to +150 c latch ? up current maximum rating per jedec standard: jesd78. 100 ma stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22 ? a114 machine model (mm) 200 v per jedec standard: jesd22 ? a115 4. the maximum package power dissipation limit must not be exceeded. 5. moisture sensitivity level (msl): 1 per ipc/jedec standard: j ? std ? 020a.
NCP5623C http://onsemi.com 5 power supply section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < vbat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 11 v bat power supply 2.7 5.5 v 10 i out continuous dc current in the load, pwm = 100% @ vf = 3.4 v, vbat = 3.0 v @ vf = 3.4 v, 3.3 v < vbat < 5.5 v 55 75 ma 10 isch continuous output short circuit current 2.85 v < vbat < 4.2 v 45 90 ma 10 vout output voltage compliance (ovp) 4.4 5.7 v 10 tstart dc/dc start time (cout = 1 f) 3.0 v < vbat = nominal < 5.5 v from last cntl positive pulse delay to full load operation 150 s 10 i stdb stand by current 3.0 v vbat 4.2 v, iout = 0 ma 0.8 1.0 a 10 i op operating current, @iout = 0 ma, 3.0 v vbat 4.2 v 350 a 3,4,5 i tol rgb output current tolerance @vbat = 3.6 v, i led = 10 ma ? 25 c < ta < 85 c 3 % 3,4,5 i match rgb output current led matching @vbat = 3.6 v, i led = 5.0 ma 0.5 % fpwr charge pump operating frequency ? 40 c < ta < 85 c 0.8 1 1.2 mhz e pwr efficiency @ vbat = 3.6 v ? led1 to led3 = 5 ma, vf = 2.8 v (total = 15 ma) ? led1 to led3 = 20 ma, vf = 3.2 v (total = 60 ma) 94.2 92.3 %
NCP5623C http://onsemi.com 6 analog section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < vbat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 8 i ref reference current @vref = 600 mv (note 7) 3 12.5 20 a 8 v ref reference voltage (note 7) ? 3% 600 +3% mv i ledr reference current (iref) current ratio 2400 8 rbias external reference current bias resistor (note 6) 30 48 200 k 3,4,5 f pwm internal pwm frequency (note 8) 2.1 khz 6. the overall output current tolerance depends upon the accuracy of the external resistor. using 1% or better resistor is recom mended. 7. the external circuit must not force the i ref pin voltage either higher or lower than the 600 mv specified. the system is optimized with a 12.5 a reference current. 8. this parameter, derived from the 1 mhz clock, is guaranteed by design, not tested in production. digital parameters section: (typical values are referenced to t a = +25 c, min & max values are referenced ? 40 c to +85 c ambient temperature, unless otherwise noted), operating conditions 2.85 v < vbat < 5.5 v, unless otherwise noted. pin symbol rating min typ max unit 9 f scl input i2c clock frequency 400 khz 7,9 v ih positive going input high voltage threshold, sda, scl signals (note 9) 1.6 v bat v 7,9 v il negative going input high voltage threshold, sda, scl signals (note 9) 0 0.4 v note: digital inputs undershoot 0.30 v to ground, digital inputs overshoot < 0.30 v to v bat 9. test guaranteed by design and fully characterized, not implemented in production. 10. the fall time ? t f ? for both scl and sda input signals must be 120 ns maximum. 2.0 v 2.7 v 4.2 v 5.5 v 3.0 v power on reset normal li ? ion maximum voltage operation operation no operation during por 7.0 v absolute maximum rating chip functionnal, but no parameter guaranteed when vbat is between 5.5 v & 7.0 v the chip might be damaged or destroyed reserved for internal reset when vbat is above 7.0 v figure 3. understanding integrated circuit voltage limitations
NCP5623C http://onsemi.com 7 dc/dc operation the converter is based on a charge pump technique to generate a dc voltage capable to supply the rgb led load. the system regulates the current flowing into each led, not the dc vout value, by means of internal current mirrors associated with the diodes. consequently, vout = vbat * mode, with mode = 1 or mode = 2, the extra voltage vout ? vf being sustained by the current mirror structure. the average forward current of each led can be independently programmed (by means of the associated pwm ) to achieve the rgb function. the maximum led current, setup by the external bias resistor connected across iref pin and ground, is associated to the digital content of the i2c register (see table 1). this peak current applies to the three led simultaneously, but, thanks to the rgb function, the average output current of each led is controlled by the independent pwm controllers. consequently, the luminosity of each rgb diode can be independently adjusted to cope with a given illumination need. since the peak current is constant, the color of the rgb diodes is the one defined by the specifications of each individual led. the built ? in ovp circuit continuously monitors the v out voltage and stops the converter when the voltage is above 5.7 v. the converter resumes to normal operation when the voltage drops below 4.4 v (no latch ? up mechanism). consequently, the chip can operate under no load conditions during any test procedures. load current calculation the load current is derived from the 600 mv reference voltage provided by the internal band gap associated to the external resistor connected across i ref pin and ground. note : due to the internal structure of this pin, no voltage, either downward or upward, shall be forced at the i ref pin. the reference current is multiplied by the constant k = 2400 to yield the output load current. since the reference voltage is based on a temperature compensated band gap, a tight tolerance resistor will provide a very accurate load current. the resistor is calculated from the ohm?s law (r bias = vref/i ref ) and a more practical equation can be arranged to define the resistor value for a given maximum output current: r bias = (vref*k)/iout [ 1 ] r bias = (0.6*2400)/iout r bias = 1440/iout [ 2 ] since the iref to iled ratio is very high, it is strongly recommended to set up the reference current at 12.5 a to optimize the tolerance of the output current. although it is possible to use higher or lower value, as defined in the analog section, a 48 k / 1% resistor will provide the best compromise, the dimming being performed by the appropriate pwm registers. on the other hand, care must be observed to avoid leakage current flowing into either the iref pin of the bias resistor network. finally, for any desired iled current, the curve provided figure 4 can be recalculated according to the equation: iled iref k 31 n (eq. 1) iled vref r 2400 31 n (eq. 2) with: n = step value @ 1 n 31 with: r = reference resistance with: k = internal multiplier constant = 2400 note: n = 0 forces iled to zero with: n = 30 and n = 31 yields the same led current load connection the primary function of the NCP5623C is to control three led arranged in the rgb color structure (reference osram latb g66x). the brightness of each led is independently controlled by a set of dedicated pwm structure embedded into the silicon chip. the peak current, identical for each led, is programmable by means of the i2c data byte. with 32 steps per pwm, the chip provides 32768 colors hue in a standard display. moreover, a built ? in gradual dimming provides a smooth brightness transition for any current level, in both upward and downward direction. the dimming function is controlled by the i2c interface: see table 2. the NCP5623C chip is capable to drive the three led simultaneously, as depicted in figure 1, but the load can be arranged to accommodate several led if necessary in the application. finally, the three current mirrors can be connected in parallel to drive a single power full led, thus yielding 90 ma current capability in a single led. i2c protocol the NCP5623C is programmed by means of the standard i2c protocol controlled by an external mcu. the communication takes place with two serial bytes sharing the same i2c frame: ? byte#1 physical i2c address ? byte#2 selected internal registers & function
NCP5623C http://onsemi.com 8 b7 b6 b5 b4 b3 b2 b1 b0 byte#1 : i2c physical address, based 7 bits : % 011 1001 $39 * 0 1 1 1 0 0 1 r/w byte#2 : data register rled2 rled1 rled0 bled4 bled3 bled2 bled1 bled0 *note: according to the i2c specifications, the physical address is based on 7 bits out of the sda byte, the 8 th bit representing the r/w command. since the NCP5623C is a receiver only, the r/w command is 0 and the hexadecimal byte send by the mcu is %0111 0010 = $72 b[7:5] : internal register selection: b7 b6 b5 function 0 0 0 chip shut down all led current = zero 0 0 1 set up the maximum output led current 0 1 0 pwm1 : led1 control 0 1 1 pwm2 : led2 control 1 0 0 pwm3 : led3 control 1 0 1 set the upward iend target 1 1 0 set the downward iend target 1 1 1 set the number of steps and activate the gradual dimming the contain of bits b[4:0] depends upon the type of function selected by bits b[7:5] as depicted in table 1 table 1. internal register bits assigment b7 b6 b5 b4 b3 b2 b1 b0 comments 0 0 0 x x x x x shut down 0 0 1 16 8 4 2 1 output led step, see figure 4 (note 11) 0 1 0 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 pwm1 0 1 1 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 pwm2 1 0 0 bpwm16 bpwm8 bpwm4 bpwm2 bpwm1 pwm3 1 0 1 gdim5 16 gdim4 8 gdim3 4 gdim2 2 gdim1 1 set gradual dimming upward iend target (note 12) 1 1 0 gdim5 16 gdim4 8 gdim3 4 gdim2 2 gdim1 1 set gradual dimming downward iend target (note 12) 1 1 1 gdim5 128 ms gdim4 64 ms gdim3 32 ms gdim2 16 ms gdim1 8 ms gradual dimming step number & run 11. the programmed current applies to the three led simultaneously, the gradual dimming is not engaged 12. the bit values represent the steps count, not the iled current: see equations 1 & 2, page 7, to derive the iled value. gradual dimming the purpose of that function is to gradually increase or decrease the brightness of the backlight led upon command from the external mcu. the function is activated and controlled by means of the i2c protocol. in order to avoid arithmetic division functions at silicon level, the period (either upward or downward) is equal to the time defined for each step, multiplied by the number of steps. to operate such a function, the mcu will provide three information: 1 ? the target current level (either upward or downward) 2 ? the time per step 3 ? the upward or downward mode of operation when a new gradual dimming sequence is requested, the output current increases, according to an exponential curve, from the existing start value to the end value. the end current value is defined by the contain of the upward or downward registers, the width of each step is defined by the third register, the number of step being in the 1 to 30 range. in the event of software error, the system checks that neither the maximum output current (30 ma), nor the zero level are forced out of their respective bounds. similarly, software errors shall not force the NCP5623C into an uncontrolled mode of operation.
NCP5623C http://onsemi.com 9 the dimming is built with 30 steps and the time delay encoded into the second byte of the i2c transaction: see table 1. when the gradual dimming is deactivated (b7 = b6 = 0, b5 = 1), the output current is straightforwardly set up to the level defined by the contain of the related register upon acknowledge of the output current byte. the gradual dimming sequence must be set up before a new output current data byte is send to the NCP5623C . at this point, the brightness sequence takes place when the new data byte is acknowledged by the internal i2c decoder. since the six registers are loaded on independent byte flow associated to the i2c address, any parameter of the NCP5623C chip can be updated ahead of the next function as depicted in table 2. table 2. basic programming sequences i2c address command bits[7:0] operation note $72 000x xxxx system shut down bits[4:0] are irrelevant $72 0010 0000 0011 1111 set up the iled current iled register bits[4:0] contain the imax value as defined by the iref value $72 0100 0000 0101 1111 set up the pwm1 pwm1 bits[4:0] contain the pwm value $72 0110 0000 0111 1111 set up the pwm2 pwm2 bits[4:0] contain the pwm value $72 1000 0000 1001 1111 set up the pwm3 pwm3 bits[4:0] contain the pwm value $72 1010 0000 1011 1111 set up the iend upward upward bits[4:0] contain the iend value $72 1100 0000 1101 1111 set up the iend downward dwnwrd bits[4:0] contain the iend value $72 1110 0000 1111 1111 set up the gradual dimming time and run the sequence grad bits[4:0] contain the time value the number of step for a given sequence, depends upon the start and end output current range: since the ipeak value is encoded in the bits[4:0] binary scale, a maximum of 31 steps is achievable during a gradual dimming operation. the number of steps will be automatically recalculated by the chip according to the equation: nstep = | existing step position ? new step position | as an example, assuming the previously programmed step was 5 and the new one is 15, then we will have 10 steps to run between the actual location to the end value. if the timing was set at 16 ms, the total gradual dimming sequence will be 160 ms. to select the direction of the gradual dimming (either upward or downward), one shall send the appropriate register before to activate the sequence as depicted below: 1010 1111 1110 0011 select an upward sequence with 24 ms/step, the end ipeak current being (iref * 2400) / (31 ? 16) ma. 1100 0001 1110 0100 select the downward sequence with 32 ms/step, the end ipeak current being (iref * 2400) / (31 ? 1) ma. table 3. output current programmed value (iled = f(step)) step iled (ma) step iled (ma) step iled (ma) step iled (ma) 0 / $00 0 9 / $09 1.25 18 / $12 2.12 27 $1b 6.90 1 / $01 0.92 10 / $0a 1.31 19 / $13 2.30 28 / $1c 9.20 2 / $02 0.95 11 / $0b 1.38 20 / $14 2.50 29 / $1d 13.80 3 / $03 0.98 12 / $0c 1.45 21 / $15 2.76 30 / $1e 27.60 4 / $04 1.02 13 / $0d 1.53 22 / $16 3.06 31 / $1f 27.60 5 / $05 1.06 14 / $0e 1.62 23 / $17 3.45 6 / $06 1.10 15 / $0f 1.72 24 / $18 3.94 7 / $07 1.15 16 / $10 1.84 25 / $19 4.60 8 / $08 1.20 17 / $11 1.97 26 / $1a 5.52 note: the table assumes i ref = 11.5 a
NCP5623C http://onsemi.com 10 figure 4. output current programmed value ( iled = f(step) ) step 35 25 20 15 10 5 0 0 15 30 i led (ma) 30 10 25 5 20 pwm operation the built ? in pwm are fully independent and can be programmed to any value during the normal operation of the NCP5623C chip. the pwm operate with five bits, yielding a 32 steps range to cover the full modulation (0 to 100%) of the associated led: ? pwm = $00 the associated led is fully off, whatever be the programmed iled value ? pwm > $00 but < $1f the brightness of the associated led is set depending upon the pwm modulation value ? pwm = $1f the associated led is fully on, the current being the one defined by the iled value. each pwm is programmable, via the i2c port as depicted, at any time under any sequence arrangement as requested by the end system?s designer. the pwm does not change the iled value, but merely modulate the on/off ratio of the associated led. each step of the pwm represent 100/32 = 3.125% of the full range, the clock being 2.1 khz (typical). figure 5. NCP5623C typical efficiency as a function of the vf v bat (v) 4.5 4.0 3.5 3.0 2.5 40 70 100 efficiency (@ 25 ma/led) (%) 50 60 90 80 vf = 3.8 v vf = 2.85 v note: efficiency is measured with the three pwm equal to 100% figure 6. basic rgb application c3 220 nf d3 d2 d1 c2 gnd c1 gnd sda r1 62 k gnd scl gnd +vbat +vcc gnd mcu i2c port c1p 1 vbat 11 agnd 6 sda 7 scl 9 iref 8 gnd 2 led1 5 led2 4 led3 3 vout 10 c1n 12 u1 NCP5623C 1 f/10 v 1 f/6.3 v gnd
NCP5623C http://onsemi.com 11 package dimensions llga12 case 513aa ? 01 issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994 . 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.20 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? ???? a d e b c 0.10 pin one 2 x reference 2 x top view side view bottom view a l d2 e2 c c 0.10 c 0.10 c 0.08 12x a1 seating plane e/2 e 11x k note 3 b 12x 0.10 c 0.05 c a b b dim min max millimeters a 0.50 0.60 a1 0.00 0.05 b 0.15 0.25 d 2.00 bsc d2 0.80 1.00 e 2.00 bsc e2 0.55 0.65 e 0.40 bsc k 0.25 ??? l 0.30 0.50 2 6 11 7 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* dimensions: millimeters l1 0.40 0.60 1 12 l1 9x 12x 0.23 2.30 0.40 pitch 0.93 0.63 0.56 11x 0.66 0.91 1 2.06 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NCP5623C/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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